In the dynamic realm of digital design, the RISC-V instruction set stands out as a symbol of innovation and progress. At semify, we're not merely adapting to this transformative wave; we're leading it, actively shaping the future. Our pivotal role in the TRISTAN project, titled "Together for RISC-V Technology and Applications," is a testament to our commitment and vision.
Our Endeavor within TRISTAN
Our focus within the TRISTAN project revolves around the CV32E40X RISC-V core maintained by the OpenHW Group. We're in the process of developing custom instructions specifically tailored for the real-time compression and decompression of digital waveforms. This initiative is set to redefine standards in processing speed and system optimization. The open-source nature of the RISC-V instruction set offers unparalleled flexibility, and we're harnessing this to craft systems that promise enhanced speed and resource efficiency. Our endgame? A fully functional ASIC, embodying our dedication to cutting-edge innovation. This ASIC is based on an Open Source tool flow provided by efabless, emphasizing our commitment to transparency and collaboration. Furthermore, the project's physical realization will employ the Skywater 130nm technology, utilizing the Open Source PDK.
As the end of November approaches, marking the delivery date for our demonstrator, we stand at a pivotal juncture in our journey. We invite you to join us, stay updated with our progress, delve deeper into the RISC-V universe, and witness firsthand the synergy between semify and the TRISTAN project. The future of digital design is here, and it's exhilarating.